Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. The storage value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
Some memory device configurations comprise multiple memory arrays, often referred to as memory planes. Various methods and systems for storing data in multi-plane memory devices are known in the art. For example, U.S. Pat. No. 7,280,398, whose disclosure is incorporated herein by reference, describes a system and method for performing memory operations in a multi-plane Flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are initiated sequentially, and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane.
U.S. Pat. No. 7,257,027, whose disclosure is incorporated herein by reference, describes a NAND-type Flash memory device having a multi-plane structure. Page buffers are divided into even page buffers and odd page buffers and are driven at the same time. Cells connected to even bit lines within one page and cell connected to odd bit lines within one page are programmed, read and copyback-programmed at the same time.
U.S. Application Publication 2006/0218359, whose disclosure is incorporated herein by reference, describes a computational system comprising a controller and a multi-plane solid state memory device accessible to the controller. The controller is configured to provide access to a virtual block having a virtual block address that represents a first block from a first plane of the multi-plane solid state memory device and represents a second block from a second plane of the multi-plane solid state memory device.